2 chipset, Cpu l1 & l2 cache [enabled, Dram clock/drive control – Asus P5V-VM DH Manuel d'utilisation
Page 69: Options de configuration: [disabled] [enabled, Options de configuration: [2] [2.5] [3, Options de configuration: [2t] [3t] [4t] [5t

ASUS P5VD2-MX/P5V-VM DH
2-21
CPU L1 & L2 Cache [Enabled]
Options de configuration: [Disabled] [Enabled]
Select Menu
Item Specific Help
Phoenix-Award BIOS CMOS Setup Utility
Advanced
Chipset
DRAM Clock/Drive Control
Frequency/Voltage control
Top Performance [Disabled]
Primary Display Adapter [PCI-E]
VGA Share Memory Size
[64M]
2.4.2 Chipset
DRAM Clock/Drive Control
Select Menu
Item Specific Help
Phoenix-Award BIOS CMOS Setup Utility
Advanced
DRAM Clock/Drive Control
Current DRAM Frequency
200MHz
DRAM Frequency
DRAM Timing Selectable
[By SPD]
x CAS Latency Time
2.5
x Bank Interleave
Disabled
x Precharge to Active(Trp)
4T
x Active to Precharge(Tras)
07T
x Active to CMD(Trcd)
4T
x REF to ACT/REF(Trfc)
20T/21T
x ACT(0) to ACT(1) (TRRD)
3T
Auto
DRAM Frequency [Auto]
Options de configuration: [Auto] [400 MHz] [533 MHz]
DRAM Timing Selectable [By SPD]
Options de configuration: [Manual] [By SPD]
Les éléments suivants ne deviennent configurables que lorsque l’option
“DRAM Timing Selectable” est réglée sur [Manual].
CAS Latency Time [2.5]
Options de configuration: [2] [2.5] [3]
Bank Interleave [Disabled]
Options de configuration: [Disabled] [2 Bank] [4 Bank] [8 Bank]
Precharge to Active(Trp) [4T]
Options de configuration: [2T] [3T] [4T] [5T]