5 chipset, Hyper threading technology [enabled, Inter(r) speedstep (tm) tech. [disabled – Asus P5B-E Plus Manuel d'utilisation
Page 89: Options de configuration : [disabled] [automatic

ASUS P5B-E Plus
4-23
North Bridge Chipset Configuration
Execute Disable Bit [Enabled]
Active ou désactive la technologie No-Execution Page Protection Définir cet
élément sur [Disabled] force le flag de la fonction XD à revenir systématiquement
sur zéro (0). Options de configuration : [Disabled] [Enabled]
Hyper Threading Technology [Enabled]
Active ou désactive la technologie Hyper Threading.
Options de configuration : [Enabled] [Disabled]
Inter(R) SpeedStep (tm) Tech. [Disabled]
Options de configuration : [Disabled] [Automatic]
4.4.5
Chipset
Le menu chipset vous permet de modifier les paramètres avancés du chipset.
Choisissez un élément et pressez <Entrée> pour afficher le sous-menu.
Select Screen
Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
v02.58 (C)Copyright 1985-2006, American Megatrends, Inc.
BIOS SETUP UTILITY
Advanced
Advanced Chipset Settings
WARMING: Setting wrong values in below sections
may cause system to malfunction.
North Bridge Configuration
South Bridge Configuration
Configure North Bridge
features.
Select Screen
Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit
v02.58 (C)Copyright 1985-2006, American Megatrends, Inc.
BIOS SETUP UTILITY
Advanced
North Bridge Chipset Configuration
Memory Remap Feature
[Disabled]
Configure DRAM Timing by SPD
[Enabled]
Static Read Control
[Auto]
Initiate Graphic Adapter
[PEG/PCI]
PEG Port Configuration
PEG Force x1
[Disabled]
PEG Link Mode
[Auto]
ENABLED: Allow
remapping of
overlapped PCI memory
above the total
physical memory.
DISABLED: Do not allow
remapping of memory